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4-channel, software-selectable, true bipolar input, 12-bit plus sign adc ad7324 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005 analog devices, inc. all rights reserved. features functional block diagram 12-bit plus sign sar adc v in 0 dout sclk cs din v drive v in 1 v in 2 v in 3 v dd refin / out v cc agnd v ss dgnd control logic and registers 13-bit successive approximation adc t/h 2.5v vref i/p mux channel sequencer ad7324 0 4864-001 true bipolar input ranges software-selectable input ranges 10 v, 5 v, 2.5 v, 0 v to +10 v 1 msps throughput rate four analog input channels with channel sequencer single-ended, true differential, and pseudo differential analog input capability high analog input impedance low power: 21 mw full power signal bandwidth: 22 mhz internal 2.5 v reference high speed serial interface power-down modes 16-lead tssop package i cmos ? process technology figure 1. general description product highlights 1. the ad7324 can accept true bipolar analog input signals, 10 v, 5 v, 2.5 v, and 0 v to +10 v unipolar signals. the ad7324 1 is a 4-channel, 12-bit plus sign, successive approximation adc designed on the i cmos (industrial cmos) process. i cmos is a process combining high voltage silicon with submicron cmos and complementary bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts could achieve. unlike analog ics using conventional cmos processes, i cmos components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. 2. the four analog inputs can be configured as four single- ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. 3. 1 msps serial interface. spi?-/qspi?-/dsp-/microwire?- compatible interface. 4. low power, 30 mw maximum, at 1 msps throughput rate. 5. channel sequencer. the ad7324 can accept true bipolar analog input signals. the ad7324 has four software-selectable input ranges, 10 v, 5 v, 2.5 v, and 0 v to +10 v. each analog input channel can be independently programmed to one of the four input ranges. the analog input channels on the ad7324 can be programmed to be single-ended, true differential, or pseudo differential. table 1. similar products selection table device number throughput rate number of channels number of bits ad7329 250 ksps 12-bit plus sign 8 the adc contains a 2.5 v internal reference. the ad7324 also allows for external reference operation. if a 3 v reference is applied to the refin/out pin, the ad7324 can accept a true bipolar 12 v analog input. minimum 12 v v dd and v ss supplies are required for the 12 v input range. the adc has a high speed serial interface that can operate at throughput rates up to 1 msps. ad7328 1000 ksps 12-bit plus sign 8 ad7327 500 ksps 12-bit plus sign 8 ad7323 500 ksps 12-bit plus sign 4 ad7322 1000 ksps 12-bit plus sign 2 ad7321 500 ksps 12-bit plus sign 2 1 protected by u.s. patent no. 6,731,232.
ad7324 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 16 circuit information.................................................................... 16 converter operation.................................................................. 16 analog input structure.............................................................. 17 typical connecti on diagram ................................................... 19 analog input ............................................................................... 19 driver amplifier choice............................................................ 21 registers ........................................................................................... 22 addressing registers .................................................................. 22 control register ......................................................................... 23 sequence register....................................................................... 25 range register ............................................................................ 25 sequencer operation ..................................................................... 26 reference ..................................................................................... 28 v drive ............................................................................................ 28 modes of operation ....................................................................... 29 normal mode.............................................................................. 29 full shutdown mode.................................................................. 29 autoshutdown mode ................................................................. 30 autostandby mode..................................................................... 30 power vs. throughput rate....................................................... 31 serial interface ................................................................................ 32 microprocessor interfacing........................................................... 33 ad7324 to adsp-218x.............................................................. 33 ad7324 to adsp-bf53x ........................................................... 33 application hints ........................................................................... 34 layout and grounding .............................................................. 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 12/05revision 0: initial version
ad7324 rev. 0 | page 3 of 36 specifications unless otherwise noted, v dd = 12 v to 16.5 v, v ss = ?12 v to ?16.5 v, v cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v to 3.0 v internal/external, f sclk = 20 mhz, f s = 1 msps, t a = t max to t min with v cc < 4.75 v, all specifications are typical. table 2. b version parameter 1 min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise ratio (snr) 2 76 db differential mode 72.5 db single-ended/pseudo differential mode signal-to-noise + distortion (sinad) 2 75 db differential mode; 2.5 v and 5 v ranges 76 db differential mode; 0 v to 10 v and 10 v ranges 72 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges 72.5 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges total harmonic distortion (thd) 2 ?80 db differential mode; 2.5 v and 5 v ranges ?82 db differential mode; 0 v to +10 v and 10 v ranges ?77 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges ?80 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges peak harmonic or spurious noise (sfdr) 2 ?80 db differential mode; 2.5 v and 5 v ranges ?82 db differential mode ; 0 v to +10 v and 10 v ranges ?78 db single-ended/pseudo differential mode; 2.5 v and 5 v ranges ?79 db single-ended/pseudo differential mode; 0 v to +10 v and 10 v ranges intermodulation distortion (imd) 2 fa = 50 khz, fb = 30 khz second-order terms ?88 db third-order terms ?90 db aperture delay 3 7 ns aperture jitter 3 50 ps common-mode rejection ratio (cmrr) 2 ?79 db up to 100 khz ripple frequency; see figure 17 channel-to-channel isolation 2 ?72 db f in on unselected channels up to 100 khz; see figure 14 full power bandwidth 22 mhz at 3 db 5 mhz at 0.1 db
ad7324 rev. 0 | page 4 of 36 b version parameter 1 min typ max unit test conditions/comments dc accuracy 4 all dc accuracy specifications are typical for 0 v to 10 v mode. resolution 13 bits no missing codes 12-bit plus sign bits differential mode 11-bit plus sign bits single-ended/pseudo differential mode integral nonlinearity 2 1.1 lsb differential mode 1 lsb single-ended/pseudo differential mode ?0.7/+1.2 lsb single-ended/pseudo differential mode (lsb = fsr/8192) differential nonlinearity 2 ?0.9/+1.5 lsb differential mode; guaranteed no missing codes to 13 bits 0.9 lsb single-ended mode; guaranteed no missing codes to 12 bits ?0.7/+1 lsb single-ended/psuedo differential mode (lsb = fsr/8192) offset error 2 , 5 ?4/+9 lsb single-ended/pseudo differential mode ?7/+10 lsb differential mode offset error match 2 , 5 0.6 lsb single-ended/pseudo differential mode 0.5 lsb differential mode gain error 2 , 5 8 lsb single-ended/pseudo differential mode 14 lsb differential mode gain error match 2 , 5 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode positive full-scale error 2 , 6 4 lsb single-ended/pseudo differential mode 7 lsb differential mode positive full-scale error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode bipolar zero error 2 , 6 8.5 lsb single-ended/pseudo differential mode 7.5 lsb differential mode bipolar zero error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode negative full-scale error 2 , 6 4 lsb single-ended/pseudo differential mode 6 lsb differential mode negative full-scale error match 2 , 6 0.5 lsb single-ended/pseudo differential mode 0.5 lsb differential mode
ad7324 rev. 0 | page 5 of 36 b version parameter 1 min typ max unit test conditions/comments analog input input voltage ranges reference = 2.5 v; see table 6 (programmed via range register) 10 v v dd = 10 v min, v ss = ?10 v min, v cc = 2.7 v to 5.25 v 5 v v dd = 5 v min, v ss = ?5 v min, v cc = 2.7 v to 5.25 v 2.5 v v dd = 5 v min, v ss = ? 5 v min, v cc = 2.7 v to 5.25 v 0 to 10 v v dd = 10 v min, v ss = agnd min, v cc = 2.7 v to 5.25 v pseudo differential v in (?) input range v dd = 16.5 v, v ss = ?16.5 v, v cc = 5 v; see figure 40 and figure 41 3.5 v reference = 2.5 v; range = 10 v 6 v reference = 2.5 v; range = 5 v 5 v reference = 2.5 v; range = 2.5 v +3/?5 v reference = 2.5 v; range = 0 v to +10 v dc leakage current 80 na v in = v dd or v ss 3 na per channel, v in = v dd or v ss input capacitance 3 13.5 pf when in track, 10 v range 16.5 pf when in track, 5 v and 0 v to +10 v ranges 21.5 pf when in track, 2.5 v range 3 pf when in hold, all ranges reference input/output input voltage range 2.5 3 v input dc leakage current 1 a input capacitance 10 pf reference output voltage 2.5 v reference output voltage error @ 25c 5 mv reference output voltage t min to t max 10 mv reference temperature coefficient 25 ppm/c 3 ppm/c reference output impedance 7 logic inputs input high voltage, v inh 2.4 v input low voltage, v inl 0.8 v v cc = 4.75 v to 5.25 v 0.4 v v cc = 2.7 to 3.6 v input current, i in 1 a v in = 0 v or v drive input capacitance, c in 3 10 pf logic outputs output high voltage, v oh v drive ? 0.2 v v i source = 200 a output low voltage, v ol 0.4 v i sink = 200 a floating-state leakage current 1 a floating-state output capacitance 3 5 pf output coding straight natural binary coding bit set to 1 in control register twos complement coding bit set to 0 in control register conversion rate conversion time 800 ns 16 sclk cycles with sclk = 20 mhz track-and-hold acquisition time 2 , 3 305 ns full-scale step input; see the terminology section throughput rate 1 msps see the serial interface section; v cc = 4.75 v to 5.25 v 770 ksps v cc < 4.75 v
ad7324 rev. 0 | page 6 of 36 b version parameter 1 min typ max unit test conditions/comments power requirements digital inputs = 0 v or v drive v dd 12 16.5 v see table 6 v ss ?12 ?16.5 v see table 6 v cc 2.7 5.25 v see table 6 ; typical specifications for v cc < 4.75 v v drive 2.7 5.25 v normal mode (static) 0.9 ma v dd /v ss = 16.5 v, v cc /v drive = 5.25 v normal mode (operational) f sample = 1 msps i dd 360 a v dd = 16.5 v i ss 410 a v ss = ?16.5 v i cc and i drive 3.2 ma v cc /v drive = 5.25 v autostandby mode (dynamic) f sample = 250 ksps i dd 200 a v dd = 16.5 v i ss 210 a v ss = ?16.5 v i cc and i drive 1.3 ma v cc /v drive = 5.25 v autoshutdown mode (static) sclk on or off i dd 1 a v dd = 16.5 v i ss 1 a v ss = ?16.5 v i cc and i drive 1 a v cc /v drive = 5.25 v full shutdown mode sclk on or off i dd 1 a v dd = 16.5 v i ss 1 a v ss = ?16.5 v i cc and i drive 1 a v cc /v drive = 5.25 v power dissipation normal mode (operational) 30 mw v dd = 16.5 v, v ss = ?16.5 v, v cc = 5.25 v 21 mw v dd = 12 v, v ss = ?12 v, v cc = 5 v full shutdown mode 38.25 w v dd = 16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 temperature range is ?40c to +85c. 2 see the terminology section. 3 sample tested during initial release to ensure compliance. 4 for dc accuracy specifications, the lsb si ze for differential mode is fsr/8192. for single-ended mode/pse udo differential mode , the lsb size is fsr/4096, unless otherwise noted. 5 unipolar 0 v to 10 v range with straight binary output coding. 6 bipolar range with twos complement output coding.
ad7324 rev. 0 | page 7 of 36 timing specifications v dd = 12 v to 16.5 v, v ss = ?12 v to ?16.5 v, v cc = 2.7 v to 5.25 v, v drive = 2.7 v to 5.25, v ref = 2.5 v to 3.0 v internal/external, t a = t max to t min . timing specifications apply with a 32 pf load, unless otherwise noted. 1 table 3. limit at t min , t max description parameter v cc < 4.75 v v cc = 4.75 v to 5.25 v unit v drive v cc f sclk 50 50 khz min 14 20 mhz max t convert 16 t sclk 16 t sclk ns max t sclk = 1/f sclk t quiet 75 60 ns min minimum time between end of serial read and next falling edge of cs t 1 12 5 ns min minimum cs pulse width t 2 2 25 20 ns min cs to sclk setup time; bipolar input ranges (10 v, 5 v, 2.5 v) 45 35 ns min unipolar input range (0 v to 10 v) t 3 26 14 ns max delay from cs until dout three-state disabled t 4 57 43 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 13 8 ns min sclk to data valid hold time t 8 40 22 ns max sclk falling edge to dout high impedance 10 9 ns min sclk falling edge to dout high impedance t 9 4 4 ns min din setup time prior to sclk falling edge t 10 2 2 ns min din hold time after sclk falling edge t power-up 750 750 ns max power up from autostandby s max 500 500 power up from full shutdown/autoshutdown mode, internal reference 25 25 s typ power up from full shutdown /autoshutdown mode, external reference 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. 2 when using v cc = 4.75 v to 5.25 v and the 0 v to 10 v unipolar range, running at 1 msps throughput rate with t 2 at 20 ns, the mark space ratio needs to be limited to 50:50. add1 12345 13141516 write reg sel1 reg sel2 lsb msb add0 sign db11 db10 db2 db1 db0 t 2 t 6 t 4 t 9 t 10 t 3 t 7 t 5 t 8 t 1 t quiet t convert sclk cs dout three- state three-state din zero 2 identification bits 04864-002 don?t care figure 2. serial interface timing diagram
ad7324 rev. 0 | page 8 of 36 absolute maximum ratings t a = 25c, unless otherwise noted table 4. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ?0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to ?16.5 v v dd to v cc v cc ? 0.3 v to 16.5 v v cc to agnd, dgnd ?0.3 v to +7 v v drive to agnd, dgnd ?0.3 v to + 7 v agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd v ss ?0.3 v to v dd + 0.3 v 1 digital input voltage to dgnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v refin to agnd ?0.3 v to v cc + 0.3 v 10 ma input current to any pin except supplies 2 operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 150.4c/w jc thermal impedance 27.6c/w pb-free temperature, soldering reflow 260(0)c esd 2.5 kv 1 if the analog inputs are being driven from alternative v dd and v ss supply circuitry, schottky diodes should be placed in series with the ad7324s v dd and v ss supplies. 2 transient currents of up to 100 ma do not cause scr latch-up. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7324 rev. 0 | page 9 of 36 pin configurations and function descriptions 04864-003 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dgnd dout v drive v in 2 v in 3 v dd v cc sclk ad7324 top view (not to scale) din dgnd agnd v in 0 v ss refin/out cs v in 1 figure 3. tssop pin configuration table 5. pin function descriptions pin no. mnemonic description 1 cs chip select. active low logic input. this input provid es the dual function of initiating conversions on the ad7324 and frames the serial data transfer. 2 din data in. data to be written to the on-chip registers is provided on this inp ut and is clocked into the register on the falling edge of sclk (see the reference section). 3, 15 dgnd digital ground. ground reference point for all digital circuitry on the ad7324. the dgnd and agnd voltages ideally should be at the same potential an d must not be more than 0.3 v apart, even on a transient basis. 4 agnd analog ground. ground reference poi nt for all analog circuitry on th e ad7324. all analog input signals and any external reference signal should be refe rred to this agnd voltage. the agnd and dgnd voltages ideally should be at the same potential an d must not be more than 0.3 v apart, even on a transient basis. 5 refin/out reference input/reference output. the on-chip reference is available on this pin for use external to the ad7324. the nominal internal reference voltage is 2.5 v, which appears at the pin. a 680 nf capacitor should be placed on the reference pin. alternatively, the internal reference can be disabled and an external reference applied to this input. on power -up, the external reference mode is the default condition (see the reference section). 6 v ss negative power supply voltage. this is the nega tive supply voltage for the analog input section. 7, 8, 10, 9 v in 0 to v in 3 analog input 0 to analog input 3. the analog inp uts are multiplexed into th e on-chip track-and-hold. the analog input channel for conversion is selected by programming the channel address bit add1 and add0 in the control register. the inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. the config- uration of the analog inputs is selected by progra mming the mode bits, bit mode 1 and bit mode 0, in the control register. the input range on each input channel is controlled by programming the range register. input ranges of 10 v, 5 v, 2.5 v, and 0 v to +10 v can be selected on each analog input channel when a +2.5 v reference voltage is used (see the reference section). 11 v dd positive power supply voltage. this is the posi tive supply voltage for the analog input section. 12 v cc analog supply voltage, 2.7 v to 5.25 v. this is the supply voltage for the adc core on the ad7324. this supply should be decoupled to agnd. specifications apply from v cc = 4.75 v to 5.25 v. 13 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltage at this pin may be different to that at v cc , but it should not exceed v cc by more than 0.3 v. 14 dout serial data output. the conversion o utput data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk inp ut, and 16 sclks are required to access the data. the data stream consists of a leading zero bit, two cha nnel identification bits, the sign bit, and 12 bits of conversion data. the data is provided msb first (see the serial interface section). 16 sclk serial clock, logic input. a serial clock input prov ides the sclk used for accessing the data from the ad7324. this clock is also used as the cl ock source for the conversion process.
ad7324 rev. 0 | page 10 of 36 typical performance characteristics 1.0 ?1.0 0 8192 code inl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 04864-007 v cc =v drive =5v t a = 25c v dd ,v ss = 15v int/ext 2.5v reference 10v range +inl = +0.55lsb ?inl = ?0.68lsb 0 ?140 0 500 frequency (khz) snr (db) ?20 ?40 ?60 ?80 ?100 ?120 50 100 150 200 250 300 350 400 450 4096 point fft v cc =v drive =5v v dd ,v ss =15v t a = 25c int/ext 2.5v reference 10v range f in = 50khz snr = 77.30db sinad = 76.85db thd = ?86.96db sfdr = ?88.22db 04864-004 figure 7. typical inl true differential mode figure 4. fft true differential mode 1.0 ?1.0 08 code dnl error (lsb) 1 9 2 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc =v drive =5v t a = 25c v dd ,v ss = 15v int/ext 2.5v reference 10v range +dnl = +0.79lsb ?dnl = ?0.38lsb 04864-043 0 ?140 0 500 frequency (khz) snr (db) ?20 ?40 ?60 ?80 ?100 ?120 50 100 150 200 250 300 350 400 450 4096 point fft v cc =v drive =5v v dd ,v ss = 15v t a =25c int/ext 2.5v reference 10v range f in = 50khz snr = 74.67db sinad = 74.03db thd = ?82.68db sfdr = ?85.40db 04864-005 figure 8. typical dnl single-ended mode figure 5. fft single-ended mode 1.0 ?1.0 08 code inl error (lsb) 1 9 2 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc =v drive =5v t a = 25c v dd ,v ss =15v int/ext 2.5v reference 10v range +inl = +0.87lsb ?inl = ?0.49lsb 04864-044 1.0 ?1.0 0 8192 code dnl error (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 v cc =v drive =5v t a =25c v dd ,v ss =15v int/ext 2.5v reference 10v range +dnl = +0.72lsb ?dnl = ?0.22lsb 04864-006 figure 6. typical dnl true differential mode figure 9. typical in l single-ended mode
ad7324 rev. 0 | page 11 of 36 ? 50 ?100 10 1000 analog input frequency (khz) thd (db) 100 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 2.5v se 2.5v diff 5v diff 5v se 10v se 10v diff 0v to +10v se v cc =5v v dd /v ss = 12v t a =25c f s =1msps 0v to +10v diff 04864-008 80 50 10 1000 analog input frequency (khz) sinad (db) 100 75 70 65 60 55 v cc =3v v dd /v ss = 12v t a = 25c f s =1msps 2.5v se 2.5v diff 5v diff 10v diff 0v to +10v se 10v se 5v se 0v to +10v diff 04864-011 figure 10. thd vs. analog input frequency for single-ended (se) and true differential mode (diff) at 5 v v cc figure 13. sinad vs. analog input frequency for single-ended (se) and differential mode (diff) at 3 v v cc ? 50 ?95 06 frequency of input noise (khz) channel-to-channel isolation (db) ? 50 ?100 10 1000 analog input frequency (khz) thd (db) 100 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 v cc =3v v dd /v ss = 12v t a =25c f s =1msps 2.5v se 2.5v diff 5v diff 5v se 10v diff 0v to +10v se 10v se 0v to +10v diff 04864-009 0 0 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 100 200 300 400 500 v dd /v ss = 12v single-ended mode f s = 1msps t a =25c 50khz on selected channel v cc =3v v cc =5v 04864-012 figure 14. channel-to-channel isolation figure 11. thd vs. analog input frequency for single-ended (se) and true differential mode (diff) at 3 v v cc 80 50 10 1000 analog input frequency (khz) sinad (db) 100 75 70 65 60 55 v cc =5v v dd /v ss = 12v t a = 25c f s =1msps 2.5v se 2.5v diff 5v diff 10v diff 5v se 0v to +10v se 10v se 0v to +10v diff 04864-010 10k 0 ?2 code number of occurrences 9k 8k 7k 6k 5k 4k 3k 2k 1k ?1 0 1 2 0 228 9469 303 0 v cc =5v v dd /v ss = 12v range = 10v 10k samples t a = 25c 04864-013 figure 12. sinad vs. analog input frequency for single-ended (se) and differential mode (diff) at 5 v v cc figure 15. histogram of codes, true differential mode
ad7324 rev. 0 | page 12 of 36 2.0 ?2.0 v dd /v ss supply voltage (v) inl error (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 5 7 9 1113151719 5v range v cc =v drive =5v internal reference single-ended mode inl = 750ksps inl = 500ksps inl = 1msps inl = 750ksps inl = 500ksps inl = 1msps 04864-050 8k 0 ?3 code number of occurences 7k 6k 5k 4k 3k 2k 1k ?2 ?1 0 1 2 3 v cc =5v v dd /v ss =12v range = 10v 10k samples t a = 25c 023 1201 7600 1165 11 0 04864-014 figure 19. inl error vs. supply voltage at 500 ksps, 750 ksps, and 1 msps figure 16. histogram of codes, single-ended mode ? 50 ?100 0 ripple frequency (khz) cmrr (db) ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 200 400 600 800 1000 1200 differential mode f in =50khz v dd /v ss = 12v f s =1msps t a =25c v cc =5v v cc =3v 0 4864-055 ? 50 ?100 0 1200 supply ripple frequency (khz) psrr (db) ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 200 400 600 800 1000 100mv p-p sine wave on each supply no decoupling single-ended mode f s =1msps v cc =5v v cc =3v v dd = 12v v ss = ?12v 04864-054 figure 17. cmrr vs. common-mode ripple frequency figure 20. psrr vs. supply ripple frequency without supply decoupling 10 1000 analog input frequency (khz) thd (db) 100 ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 v cc =v drive =5v v dd /v ss = 12v t a = 25c internal reference range = 10v and 2.5v r in =50 ? , 2.5v range r in =50 ? , 10v range r in = 100 ? , 2.5v range r in = 1000 ? , 2.5v range r in = 2000 ? , 2.5v range r in = 4700 ? , 2.5v range r in =2000 ? , 10v range r in = 1000 ? , 10v range r in =100 ? , 10v range 04864-015 2.0 ?2.0 v dd /v ss supply voltage (v) dnl error (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 5 7 9 11 13 15 17 19 5v range v cc =v drive =5v internal reference single-ended mode dnl = 750ksps dnl = 750ksps dnl = 500ksps dnl = 500ksps dnl = 1msps dnl = 1msps 04864-049 figure 21. thd vs. analog input frequency for various source impedances, true differential mode figure 18. dnl error vs. supply voltage at 500 ksps, 750 ksps, and 1 msps
ad7324 rev. 0 | page 13 of 36 10 1000 input frequency (khz) thd (db) 100 ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 v cc =v drive =5v v dd /v ss = 12v t a = 25c internal reference range = 10v and 2.5v r in =2000 ? , 10v range r in = 1000 ? , 10v range r in =50 ? , 2.5v range r in = 100 ? , 10v range r in = 100 ? , 2.5v range r in = 1000 ? , 2.5v range r in = 2000 ? , 2.5v range r in =50 ? , 10v range 04864-016 figure 22. thd vs. analog input frequency for various source impedances, single-ended mode
ad7324 rev. 0 | page 14 of 36 terminology differential nonlinearity negative full-scale error this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. this applies when using twos complement output coding and any of the bipolar analog input ranges. this is the deviation of the first code transition (10 000) to (10 001) from the ideal (that is, ?4 v ref + 1 lsb, ?2 v ref + 1 lsb, ?v ref + 1 lsb) after adjusting for the bipolar zero code error. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (a point 1 lsb below the first code transition) and full scale (a point 1 lsb above the last code transition). negative full-scale error match this is the difference in negative full-scale error between any two input channels. offset code error track-and-hold acquisition time this applies to straight binary output coding. it is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, agnd + 1 lsb. the track-and-hold amplifier returns into track mode after the 14 th sclk rising edge. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of a conversion. for the 2.5v range, the specified acquisition time is the time required for the track-and-hold amplifier to settle to within 1 lsb. offset error match this is the difference in offset error between any two input channels. signal to (noise + distortion) ratio gain error this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digi- tization process. the more levels, the smaller the quantization noise. theoretically, the signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by this applies to straight binary output coding. it is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 v ref ? 1 lsb, 2 v ref ? 1 lsb, v ref ? 1 lsb) after adjusting for the offset error. gain error match this is the difference in gain error between any two input channels. signal to ( noise + distortion ) = (6.02 n + 1.76) db bipolar zero code error this applies when using twos complement output coding and a bipolar analog input. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, agnd ? 1 lsb. for a 13-bit converter, this is 80.02 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7324, it is defined as bipolar zero code error match 1 2 6 2 5 2 4 2 3 2 2 log20)db( v vvvvv thd ++++ = this refers to the difference in bipolar zero code error between any two input channels. where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. positive full-scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. it is the deviation of the last code transition (011 110) to (011 111) from the ideal (4 v ref ? 1 lsb, 2 v ref ? 1 lsb, v ref ? 1 lsb) after adjusting for the bipolar zero code error. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak. positive full-scale error match this is the difference in positive full-scale error between any two input channels.
ad7324 rev. 0 | page 15 of 36 channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale, 100 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 khz signal. figure 14 shows the worst- case across all eight channels for the ad7324. the analog input range is programmed to be the same on all channels. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second-order terms include (fa + fb) and (fa ? fb), whereas the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7324 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. psr (power supply rejection) variations in power supply affect the full-scale transition but not the linearity of the converter. power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the typical performance characteristics section). cmrr (common-mode rejection ratio) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv sine wave applied to the common-mode voltage of the vin+ and vin? frequency, f s , as cmrr (db) = 10 log ( pf / pf s ) where pf is the power at frequency f in the adc output, and pf s is the power at frequency f s in the adc output (see figure 17 ).
ad7324 rev. 0 | page 16 of 36 theory of operation circuit information the analog inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. selection can be made by programming the mode bits, mode 0 and mode 1, in the control register. the ad7324 is a fast, 4-channel, 12-bit plus sign, bipolar input, serial a/d converter. the ad7324 can accept bipolar input ranges that include 10 v, 5 v, and 2.5 v; it can also accept a 0 v to +10 v unipolar input range. a different analog input range can be programmed on each analog input channel via the on-chip registers. the ad7324 has a high speed serial interface that can operate at throughput rates up to 1 msps. the serial clock input accesses data from the part and provides the clock source for the successive approximation adc. the ad7324 has an on-chip 2.5 v reference. however, the ad7324 can also work with an external reference. on power-up, the external reference operation is the default option. if the internal reference is the preferred option, the user must write to the reference bit in the control register to select the internal reference operation. the ad7324 requires v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than the analog input range. see table 6 for the requirements of these supplies for each analog input range. the ad7324 requires a low voltage 2.7 v to 5.25 v v cc supply to power the adc core. table 6. reference and supply requirements for each analog input range the ad7324 also features power-down options to allow power saving between conversions. the power-down modes are selected by programming the on-chip control register as described in the selected analog input range (v) reference voltage (v) full-scale input range (v) minimum v dd /v ss (v) av cc (v) modes of operation section. 2.5 10 3/5 10 10 3.0 12 3/5 converter operation 12 2.5 5 3/5 5 5 the ad7324 is a successive approximation analog-to-digital converter built around two capacitive dacs. 3.0 6 3/5 6 figure 23 and 2.5 2.5 3/5 5 2.5 figure 24 show simplified schematics of the adc in single- ended mode during the acquisition and conversion phases, respectively. 3.0 3 3/5 5 2.5 0 to +10 3/5 +10/agnd 0 to +10 3.0 0 to +12 3/5 +12/agnd figure 25 and figure 26 show simplified schematics of the adc in differential mode during acquisition and conversion phases, respectively. the adc is composed of control logic, a sar, and capacitive dacs. in to meet the specified performance specifications when the ad7324 is configured with the minimum v dd and v ss supplies for a chosen analog input range, the throughput rate should be decreased from the maximum throughput range (see the figure 23 (the acquisition phase), sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input. typical performance characteristics section). figure 18 and figure 19 show the change in inl and dnl as the v dd and v ss voltages are varied. when operating at the maximum throughput rate, as the v dd and v ss supply voltages are reduced, the inl and dnl error increases. however, as the throughput rate is reduced with the minimum v dd and v ss supplies, the inl and dnl error is reduced. capacitive dac control logic comparator agnd sw2 sw1 a b c s v in 0 04864-017 figure 31 shows the change in thd as the v dd and v ss supplies are reduced. at the maximum throughput rate, the thd degrades significantly as v dd and v ss are reduced. it is therefore necessary to reduce the throughput rate when using minimum v dd and v ss supplies so that there is less degradation of thd and the specified performance can be maintained. the degradation is due to an increase in the on resistance of the input multiplexer when the v dd and v ss supplies are reduced. figure 23. adc acquisition phase (single-ended) when the adc starts a conversion ( figure 24 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the capacitive dac to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code.
ad7324 rev. 0 | page 17 of 36 capacitive dac control logic comparator agnd sw2 sw1 a b c s v in 0 0 4864-018 the ideal transfer characteristic for the ad7324 when twos complement coding is selected is shown in figure 27 . the ideal transfer characteristic for the ad7324 when straight binary coding is selected is shown in figure 28 . 011...111 011...110 000...001 000...000 111...111 ?fsr/2 + 1lsb agnd + 1lsb +fsr/2 ? 1lsb bipolar ranges +fsr ? 1lsb unipolar range agnd ? 1lsb analog input adc code 100...010 100...001 100...000 04864-021 figure 24. adc conversion phase (single-ended) figure 25 shows the differential configuration during the acquisition phase. for the conversion phase, sw3 opens and sw1 and sw2 move to position b ( figure 26 ). the output impedances of the source driving the v in + and v in ? pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? v ref 04864-019 figure 27. twos complement transfer characteristic (bipolar ranges) 111...111 111...110 111...000 011...111 ?fsr/2 + 1lsb agnd + 1lsb +fsr/2 ? 1lsb bipolar ranges +fsr ? 1lsb unipolar range analog input adc code 000...010 000...001 000...000 04864-022 figure 25. adc differential configuration during acquisition phase capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? v ref 04864-020 figure 28. straight binary transfer characteristic (bipolar ranges) analog input structure the analog inputs of the ad7324 can be configured as single- ended, true differential, or pseudo differential via the control register mode bits (see table 10 ). the ad7324 can accept true bipolar input signals. on power-up, the analog inputs operate as four single-ended analog input channels. if true differential or pseudo differential is required, a write to the control register is necessary after power-up to change this configuration. figure 26. adc differential configuration during conversion phase output coding the ad7324 default output coding is set to twos complement. the output coding is controlled by the coding bit in the control register. to change the output coding to straight binary coding, the coding bit in the control register must be set. when operating in sequence mode, the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register. figure 29 shows the equivalent analog input circuit of the ad7324 in single-ended mode. figure 30 shows the equivalent analog input structure in differential mode. the two diodes provide esd protection for the analog inputs. d d v dd c2 r1 v in 0 v ss c1 04864-023 transfer functions the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size is dependent on the analog input range selected. table 7. lsb sizes for each analog input range figure 29. equivalent analog input circuit (single-ended) input range full-scale range/8192 codes lsb size 10 v 20 v 2.441 mv 5 v 10 v 1.22 mv 2.5 v 5 v 0.61 mv 0 v to +10 v 10 v 1.22 mv
ad7324 rev. 0 | page 18 of 36 d d v dd c2 r1 v in + v ss c1 d d v dd c2 r1 v in ? v ss c1 04864-024 the ad7324 enters track mode on the 14 th sclk rising edge. when running the ad7324 at a throughput rate of 1 msps with a 20 mhz sclk signal, the adc has approximately 1.5 sclk + t8 + t quiet to acquire the analog input signal. the adc goes back into hold mode on the cs falling edge. as the v dd /v ss supply voltage is reduced, the on resistance of the input multiplexer increases. therefore, based on the equation for t acq , it is necessary to increase the amount of acquisition time provided to the ad7324 and, hence, decrease the overall throughput rate. figure 30. equivalent analog input circuit (differential) figure 31 shows that if the throughput rate is reduced when operating with minimum v dd and v ss supplies, the specified thd performance is maintained. care should be taken to ensure that the analog input does not exceed the v dd and v ss supply rails by more than 300 mv. exceeding this value causes the diodes to become forward biased and to start conducting into either the v dd supply rail or v ss supply rail. these diodes can conduct up to 10 ma without causing irreversible damage to the part. ? 50 ?95 51 v dd /v ss supplies (v) thd (db) 9 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 7 9 11 13 15 17 500ksps 750ksps 1msps v cc =v drive =5v internal reference t a =25c f in = 10khz 5v range se mode 0 4864-051 figure 29 and figure 30 in , capacitor c1 is typically 4 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of the input multiplexer and the track-and-hold switch. capacitor c2 is the sampling capacitor; its capacitance varies depending on the analog input range selected (see the specifications section). track-and-hold section the track-and-hold on the analog input of the ad7324 allows the adc to accurately convert an input sine wave of full-scale amplitude to 13-bit accuracy. the input bandwidth of the track- and-hold is greater than the nyquist rate of the adc. the ad7324 can handle frequencies up to 22 mhz. figure 31. thd vs. v dd /v ss supply voltage at 500 ksps, 750 ksps, and 1 msps unlike other bipolar adcs, the ad7324 does not have a resistive analog input structure. on the ad7324, the bipolar analog signal is sampled directly onto the sampling capacitor. this gives the ad7324 high analog input impedance. an approximation for the analog input impedance can be calculated from the following formula: the track-and-hold enters its tracking mode on the 14 th sclk rising edge after the cs falling edge. the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. with 0 source impedance, 305 ns is sufficient to acquire the signal to the 13-bit level. the acquisition time required is calculated using the following formula: z = 1/(f s c s ) where f s is the sampling frequency, and c s is the sampling capacitor value. t acq = 10 (( r source + r ) c ) where c is the sampling capacitance and r is the resistance seen by the track-and-hold amplifier looking back on the input. for the ad7324, the value of r includes the on resistance of the input multiplexer and is typically 300 . r source should include any extra source impedance on the analog input. c s depends on the analog input range chosen (see the specifications section). when operating at 1 msps, the analog input impedance is typically 75 k for the 10v range. as the sampling frequency is reduced, the analog input impedance further increases. as the analog input impedance increases the current required to drive the analog input therefore decreases.
ad7324 rev. 0 | page 19 of 36 ad7324 1 v in + v + v? v dd v ss v cc 5v agnd 1 additional pins omitted for clarity. 04864-026 typical connection diagram figure 32 shows a typical connection diagram for the ad7324. in this configuration, the agnd pin is connected to the analog ground plane of the system, and the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the ad7324 can be configured to operate in single-ended, true differential, or pseudo differential mode. the ad7324 can operate with either an internal or external reference. in figure 32 , the ad7324 is configured to operate with the internal 2.5 v reference. a 680 nf decoupling capacitor is required when operating with the internal reference. figure 33. single-ended mode typical connection diagram true differential mode the v cc pin can be connected to either a 3 v supply voltage or a 5 v supply voltage. the v dd and v ss are the dual supplies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels (see the ad7324 can have a total of two true differential analog input pairs. differential signals have some benefits over single- ended signals, including better noise immunity based on the devices common-mode rejection and improvements in distortion performance. tabl e 6 ). the v drive pin is connected to the supply voltage of the microprocessor. the voltage applied to the v drive input controls the voltage of the serial interface. v drive can be set to 3 v or 5 v. figure 34 defines the configuration of the true differential analog inputs of the ad7324. ad7324 1 v in + v in ? 1 additional pins omitted for clarity. 04864-027 ad7324 v cc v dd 1 serial interface c/p v in 0 v in 1 v in 2 v in 3 refin/out cs dout v drive sclk din dgnd 10f 0.1f + 10f 0.1f + 10f 0.1f + analog inputs 10v,5v,2.5v 0v to +10v +15 v ?15v 680nf v ss 1 v cc +2.7 v to +5.25 v 1 minimum v dd and v ss supply voltages depend on the highest analog input range selected. agnd 10f 0.1f + +3v supply 04864-025 figure 34. true differential inputs the amplitude of the differential signal is the difference between the signals applied to the v in + and v in ? pins in each differential pair (v in + ? v in ?). v in + and v in ? should be simultaneously driven by two signals of equal amplitude, dependent on the input range selected, that are 180 out of phase. assuming the 4 v ref mode, the amplitude of the differential signal is ?20 v to +20 v p-p (2 4 v ref ), regardless of the common mode. the common mode is the average of the two signals figure 32. typical connection diagram ( vin + + vin ?)/2 analog input and is therefore the voltage on which the two input signals are centered. single-ended inputs the ad7324 has a total of four analog inputs when operating in single-ended mode. each analog input can be independently programmed to one of the four analog input ranges. in applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the adc analog inputs. this voltage is set up externally, and its range varies with reference voltage. as the reference voltage increases, the common-mode range decreases. when driving the differential inputs with an amplifier, the actual common mode range is determined by the amplifiers output swing. if the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the v dd supply pin and the v ss supply pin. figure 33 shows the configuration of the ad7324 in single- ended mode. when a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude ?2 (4 v ref ) to +2 (4 v ref ) corresponding to digital codes ?4096 to +4095.
ad7324 rev. 0 | page 20 of 36 16.5v v dd /v ss 12v v dd /v ss 5 ?6 v com range (v) 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 v cc =3v v ref =3v 2.5v range 10v range 5v range 2.5v range 5v range 10v range 04864-045 8 ?8 6 4 2 0 ?2 ?4 ?6 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc =5v v ref =2.5v 2.5v range 10v range 5v range 2.5v range 5v range 10v range 04864-048 figure 35. common-mode range for v cc = 3 v and refin/out = 3 v figure 38. common-mode range for v cc = 5 v and refin/out = 2.5 v 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc =5v v ref =3v 8 ?4 6 4 2 0 ?2 2.5v range 10v range 5v range 2.5v range 5v range 10v range 04864-046 pseudo differential inputs the ad7324 can have two pseudo differential pairs or three pseudo differential inputs referenced to a common v in ? pin. the v in + inputs are coupled to the signal source and must have an amplitude within the selected range for that channel as programmed in the range register. a dc input is applied to the v in ? pin. the voltage applied to this input provides an offset for the v in + input from ground or a pseudo ground. pseudo differential inputs separate the analog input signal ground from the adc ground, allowing cancellation of dc common-mode voltages. figure 39 shows the ad7328 configured in pseudo differential mode. when a conversion takes place, the pseudo ground corresponds to code ?4096 and the maximum amplitude corresponds to code +4095. figure 36. common-mode range for v cc = 5 v and refin/out = 3 v 6 ?8 4 2 0 ?2 ?4 ?6 16.5v v dd /v ss 12v v dd /v ss v com range (v) v cc =3v v ref =2.5v 2.5v range 10v range 5v range 2.5v range 5v range 10v range 04864-047 ad7324 1 v in + v + v? v dd v ss v cc 5v 1 additional pins omitted for clarity. v in ? 04864-028 figure 39. pseudo differential inputs figure 37. common-mode range for v cc = 3 v and refin/out = 2.5 v figure 40 and figure 41 show the typical voltage range on the v in ? pin for the different analog input ranges when configured in the pseudo differential mode. for example, when the ad7324 is configured to operate in pseudo differential mode and the 5 v range is selected with 16.5 v v dd /v ss supplies and 5 v v cc , the voltage on the v in ? pin can vary from ?6.5 v to +6.5 v.
ad7324 rev. 0 | page 21 of 36 8 ? 8 6 4 2 0 ? 2 ? 4 ? 6 2.5v range 10v range 10v range 5v range 2.5v range 5v range 0v to +10v range 0v to +10v range 16.5v v dd /v ss 12v v dd /v ss 04864-039 v cc =5v v ref =2.5v the driver amplifier must be able to settle for a full-scale step to a 13-bit level, 0.0122%, in less than the specified acquisition time of the ad7324. an op amp such as the ad8021 meets this requirement when operating in single-ended mode. the ad8021 needs an external compensating npo type of capacitor. the ad8022 can also be used in high frequency applications where a dual version is required. for lower frequency applications, op amps such as the ad797, ad845, and ad8610 can be used with the ad7324 in single-ended mode configuration. differential operation requires that v in + and v in ? be simultaneously driven with two signals of equal amplitude that are 180 out of phase. the common mode must be set up externally to the ad7324. the common-mode range is determined by the refin/out voltage, the v cc supply voltage, and the particular amplifier used to drive the analog inputs. differential mode with either an ac input or a dc input provides the best thd performance over a wide frequency range. because not all applications have a signal preconditioned for differential operation, there is often a need to perform the single-ended-to- differential conversion. figure 40. pseudo input range with v cc = 5 v 2.5v range 10v range 10v range 5v range 2.5v range 5v range 0v to +10v range 0v to +10v range 16.5v v dd /v ss 12v v dd /v ss 4 ?8 2 0 ?2 ?4 ?6 04864-040 v cc =3v v ref =2.5v this single-ended-to-differential conversion can be performed using an op amp pair. typical connection diagrams for an op amp pair are shown in figure 42 and figure 43 . in figure 42 , the common-mode signal is applied to the noninverting input of the second amplifier. v in v+ v? 3k ? 1.5k ? 1.5k ? 1.5k ? 1.5k ? 10k ? 20k ? v com 04864-029 figure 41. pseudo input range with v cc = 3 v driver amplifier choice in applications where the harmonic distortion and signal-to- noise ratio are critical specifications, the analog input of the ad7324 should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and can necessitate the use of an input buffer amplifier. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated in the application. the thd increases as the source impedance increases and performance degrades. figure 42. single-ended-to-different ial configuration with the ad845 v in v+ v? 442 ? 442 ? 442 ? 442 ? 442 ? 100? ad8021 ad8021 442? 04864-030 figure 21 and figure 22 show graphs of the thd vs. the analog input frequency for various source impedances. depending on the input range and analog input configuration selected, the ad7324 can handle source impedances of up to 4.7 k before the thd starts to degrade. due to the programmable nature of the analog inputs on the ad7324, the choice of op amp used to drive the inputs is a function of the particular application and depends on the input configuration and the analog input voltage ranges selected. figure 43. single-ended-to-different ial configuration with the ad8021
ad7324 rev. 0 | page 22 of 36 registers the ad7324 has three programmable registers, the control register, the sequence register, and the range register. these registe rs are write- only registers. addressing registers a serial transfer on the ad7324 consists of 16 sclk cycles. the three msbs on the din line during the 16 sclk transfer are deco ded to determine which register is addressed. the three msbs consist of the write bit, register select 1 bit, and register select 2 bi t. the register select bits are used to determine which of the three on-board registers is selected. the write bit determines if the data on th e din line following the register select bits loads into the addressed register. if the write bit is 1, the bits load into the register ad dressed by the register select bits. if the write bit is 0, the data on the din line does not load into any register. table 8. decoding register select bits and write bit write register select 1 register select 2 comment 0 0 0 data on the din line during this serial transfer is ignored. 1 0 0 this combination selects the control register. the subsequent 12 bits are loaded into the control register. 1 0 1 this combination selects the range register. the subsequent 8 bits are loaded into the range register. 1 1 1 this combination selects the sequence register. the subsequent 4 bits are loaded into the sequence register.
ad7324 rev. 0 | page 23 of 36 control register the control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. the control register is a write-only, 12-bit register. data loaded on the din line corresponds to the ad7324 configuration for the next conversion. if the sequence register is being used, data should be loaded into the control register after the range register an d the sequence register have been initialized. the bit functions of the control register are shown in table 9 (the power-up status of all bits is 0). msb lsb 15 14 13 12 11 10 9 8 7 6 5 1 3 2 1 0 write register select 1 register select 2 zero add1 add0 mode 1 mode 0 pm1 pm0 coding ref seq1 seq2 zero 0 table 9. control register details bit mnemonic description 12, 1 zero a 0 must be written to this bit to ensure correct operation of the device 11, 10 add1, add0 these two channel address bits are used to select the analog input channel for the next conversion if the sequencer is not being used. if the sequencer is be ing used, the two channel address bits are used to select the final channel in a consecutive sequence. 9, 8 mode 1, mode 0 these two mode bits are used to select the co nfiguration of the four analog input pins, v in 0 to v in 3. these pins are used in conjunction with the channel address bits. on the ad7324, the analog inputs can be configured as four single-ended inputs, two true differ ential input pairs, two pseu do differential inputs, or three pseudo differential inputs (see table 10 ). 7, 6 pm1, pm0 the power management bits are used to select different power mode options on the ad7324 (see table 11 ). 5 coding this bit is used to select the ty pe of output coding the ad7324 uses for the next conversion result. if coding = 0, the output coding is twos complement. if coding = 1, the output coding is straight binary. when operating in sequence mode, the output coding fo r each channel is the value written to the coding bit during the last write to the control register. 4 ref the reference bit is used to enable or disable the internal reference. if ref = 0, the external reference is enabled and used for the next conversion, and the internal reference is disabled. if ref = 1, the internal reference is used for the next conversion. when operating in sequence mode, the reference used for each channel is the value written to the ref bit during the last write to the control register. 3, 2 seq1, seq2 the sequence 1 and sequence 2 bits are used to control the operation of the sequencer (see table 12 ). the four analog input channels can be configured as three pseudo differential analog inputs, two pseudo differential inputs, tw o true differential input pairs, or four single-ended analog inputs. table 10. analog input configuration selection mode 1 = 1, mode 0 = 1 mode 1 = 1, mode 0 = 0 mode 1 = 0, mode 0 =1 mode 1 = 0, mode 0 = 0 channel address bits 3 pseudo differential i/ps 2 fully differ ential i/ps 2 pseudo differenti al i/ps 4 single-ended i/ps add1 add0 v in + v in ? v in + v in ? v in + v in ? v in + v in ? 0 0 v in 0 v in 3 v in 0 v in 1 v in 0 v in 1 v in 0 agnd 0 1 v in 1 v in 3 v in 0 v in 1 v in 0 v in 1 v in 1 agnd 1 0 v in 2 v in 3 v in 2 v in 3 v in 2 v in 3 v in 2 agnd 1 1 not a valid selection v in 2 v in 3 v in 2 v in 3 v in 3 agnd
ad7324 rev. 0 | page 24 of 36 table 11. power mode selection pm1 pm0 description 1 1 full shutdown mode. in this mode, all internal circuitry on the ad7324 is powered down. information in the control register is retained when the ad7324 is in full shutdown mode. 1 0 autoshutdown mode. the ad7324 en ters autoshutdown on the 15 th sclk rising edge when the control register is updated. all internal circuitry is powered down in autoshutdown. 0 1 autostandby mode. in this mode, all internal circuitry is po wered down excluding the internal reference. the ad7324 enters autostandby mode on the 15 th sclk rising edge after the control register is updated. 0 0 normal mode. all internal circui try is powered up at all times. table 12. sequencer selection seq1 seq2 sequence type 0 0 the channel sequencer is not used. the analog channel, se lected by programming the add1 bit and add0 bit in the control register, selects the next channel for conversion. 0 1 uses sequence of channels that were previously programmed in the sequence register for conversion. the ad7324 starts converting on the lowest channel in the sequence. the channe ls are converted in ascending order. if uninterrupted, the ad7324 keeps converting the sequence. the range for each cha nnel defaults to the range previously written into the range register. 1 0 used in conjunction with the channel address bits in the control register. this allows continuous conversions on a consecutive sequence of channels, from ch annel 0 up to and including a final channel selected by the channel address bits in the control register. the range for each channel defaults to the range previously written into the range register. 1 1 the channel sequencer is not used. the analog channel, se lected by programming the add1 bit and add0 bit in the control register, selects the next channel for conversion.
ad7324 rev. 0 | page 25 of 36 sequence register the sequence register on the ad7324 is a 4-bit, write-only register. each of the four analog input channels has one correspondi ng bit in the sequence register. to select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequenc e register. msb lsb 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 write register select 1 register select 2 v in 0 v in 1 v in 2 v in 3 0 0 0 0 0 0 0 0 0 range register the range register is used to select one analog input range per analog input channel. it is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from channel 0 to channel 3. there are four analog input ranges, 10 v, 5 v, 2.5 v, and 0 v to +10 v. a write to the range register is selected by setting the write bit to 1 and the register select bits to 0 and 1. after the initial write to the range register occurs, each time an analog input is selected, the ad7324 automatically configures the analog input to the a ppropriate range, as indicated by the range register. the 10 v input range is selected by default on each analog input channel (see table 1 3 ). msb lsb 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 write register select 1 register select 2 v in 0a v in 0b v in 1a v in 1b v in 2a v in 2b v in 3a v in 3b 0 0 0 0 0 table 13. range selection v in xa v in xb description 0 0 this combination selects the 10 v input range on v in x. 0 1 this combination selects the 5 v input range on v in x. 1 0 this combination selects the 2.5 v input range on v in x. 1 1 this combination selects the 0 v to +10 v input range on v in x.
ad7324 rev. 0 | page 26 of 36 sequencer operation din: write to range register to select the range for each analog input channel. dout: conversion result from channel 0, 10v range, single-ended mode. cs din: tie din low/write bit = 0 to continue to convert through the sequence of channels. dout: conversion result from first channel in the sequence. cs din: write to sequence register to select the new sequence. dout: conversion result from channel x in the first sequence. cs din: write to control register to start the sequence, seq1 = 0, seq2 = 1. dout: conversion result from channel 0, single-ended mode, range selected in range register. cs din: write to sequence register to select the analog input channels to be included in the sequence. dout: conversion result from channel 0, single-ended mode, range selected in range register. cs power on. continuously convert on the selected sequence of channels. din tied low/write bit = 0. selecting a new sequence. din: write to control register to stop the sequence, seq1 = 0, seq2 = 0. dout: conversion result from channel in sequence. cs stopping a sequence. 0 4864-031 figure 44. programmable sequence flowchart the ad7324 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register with the seq1 bit and the seq2 bit in the control register. this initial serial transfer is only necessary if input ranges other than the default ranges are required. after the analog input ranges are configured, a write to the sequence register is necessary to select the channels to be included in the sequence. once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting seq1 to 0 and seq2 to 1. the ad7324 continues to convert the selected sequence without interruption provided that the sequence register remains unchanged, and seq1 = 0 and seq2 = 1 in the control register. figure 44 shows how to program the ad7324 register to operate in sequence mode. after power-up, all of the three on-chip registers contain default values. each analog input has a default input range of 10 v. if different analog input ranges are required, a write to the range register is required. this is shown in the first serial transfer of figure 44 .
ad7324 rev. 0 | page 27 of 36 once the control register is configured to operate the ad7324 in this mode, the din line can be held low, or the write bit can be set to 0. to return to traditional multichannel operation, a write to the control register to set seq1 to 0 and seq2 to 0 is necessary. if a change to the range register is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting seq1 to 0 and seq2 to 0. next, the write to the range register should be completed to change the required range. the previously selected sequence should then be initiated again by writing to the control register and setting seq1 to 0 and seq2 to 1. the adc converts on the first channel in the sequence. when the seq1 and seq2 are both set to 0, or when both are set to 1, the ad7324 is configured to operate in traditional multi- channel mode, where a write to channel address bit add1 to bit add0 in the control register selects the next channel for conversion. the ad7324 can be configured to convert a sequence of consecutive channels (see figure 45 ). this sequence begins by converting on channel 0 and ends with a final channel as selected by bit add1 to bit add0 in the control register. in this configuration, there is no need for a write to the sequence register. to operate the ad7324 in this mode, set seq1 to 1 and seq2 to 0 in the control register, and then select the final channel in the sequence by programming bit add1 to bit add0 in the control register. 04864-032 din: write to range register to select the range for analog input channels. dout: conversion result from channel 0, 10v range, single-ended mode. c s din: write bit = 0 or din line held low to continue through sequence of consecutive channels. dout: conversion result from channel 1, range selected in range register. c s din: write bit = 0 or din line held low to continue to convert through the sequence of consecutive channels. dout: conversion result from channel 0, range selected in range register. c s din: write to control register to select the final channel in the consecutive sequence, set seq1 = 1 and seq2 = 0. select output coding for sequence. dout: conversion result from channel 0, range selected in range register, single-ended mode. c s power on. dintiedlow/writebit=0. continuously convert on consecutive sequence of channels. din: write to control register to stop the sequence, seq1 = 0, seq2 = 0. dout: conversion result from channel in sequence. cs stopping a sequence. figure 45. flowchart for consecutive sequence of channels
ad7324 rev. 0 | page 28 of 36 reference the ad7324 can operate with either the internal 2.5 v on-chip reference or an externally applied reference. the internal reference is selected by setting the ref bit in the control register to 1. on power-up, the ref bit is 0, selecting the external reference for the ad7324 conversion. suitable reference sources for the ad7324 include ad780, ad1582, adr431, ref193, and adr391. the internal reference circuitry consists of a 2.5 v band gap reference and a reference buffer. when operating the ad7324 in internal reference mode, the 2.5 v internal reference is available at the refin/out pin, which should be decoupled to agnd using a 680 nf capacitor. it is recommended that the internal reference be buffered before applying it elsewhere in the system. the internal reference is capable of sourcing up to 90 a. on power-up, if the internal reference operation is required for the adc conversion, a write to the control register is necessary to set the ref bit to 1. during the control register write, the conversion result from the first initial conversion is invalid. the reference buffer requires 500 s to power up and charge the 680 nf decoupling capacitor during the power-up time. the ad7324 is specified for a 2.5 v to 3 v reference range. when a 3 v reference is selected, the ranges are 12 v, 6 v, 3 v, and 0 v to +12 v. for these ranges, the v dd and v ss supply must be equal to or greater than the maximum analog input range selected, see table 6 . v drive the ad7324 has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7324 is operated with a v cc of 5 v, the v drive pin can be powered from a 3 v supply. this allows the ad7324 to accept large bipolar input signals with low voltage digital processing.
ad7324 rev. 0 | page 29 of 36 modes of operation the ad7324 has several modes of operation that are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. the mode of operation of the ad7324 is controlled by the power manage- ment bits, bit pm1 and bit pm0, in the control register as shown in the ad7324 remains fully powered up at the end of the conversion if both pm1 and pm0 contain 0 in the control register. to complete the conversion and access the conversion result 16 serial clock cycles are required. at the end of the conversion, cs can idle either high or low until the next conversion. table 11 . the default mode is normal mode, where all internal circuitry is fully powered up. once the data transfer is complete, another conversion can be initiated after the quiet time, t quiet , has elapsed. normal mode (pm1 = pm0 = 0) full shutdown mode (pm1 = pm0 = 1) this mode is intended for the fastest throughput rate performance, with the ad7324 being fully powered up at all times. in this mode, all internal circuitry on the ad7324 is powered down. the part retains information in the registers during full shutdown. the ad7324 remains in full shutdown mode until the power management bits, bit pm1 and bit pm0, in the control register are changed. figure 46 shows the general operation of the ad7324 in normal mode. the conversion is initiated on the falling edge of cs , and the track-and-hold enters hold mode as described in the serial interface section. data on the din line during the 16 sclk transfer is loaded into one of the on-chip registers if the write bit is set. the register is selected by programming the register select bits (see a write to the control register with pm1 = 1 and pm0 = 1 places the part into full shutdown mode. the ad7324 enters full shut- down mode on the 15 th sclk rising edge rising edge once the control register is updated. figure 46 ). 1 1 6 leading zero, 2 channel i.d. bits, sign bit + conversion result data into control/sequence/range register sclk cs dout din 0 4864-035 if a write to the control register occurs while the part is in full shutdown mode with the power management bits, bit pm1 and bit pm0, set to 0 (normal mode), the part begins to power up on the 15 th sclk rising edge once the control register is updated. figure 47 shows how the ad7324 is configured to exit full shutdown mode. to ensure the ad7324 is fully powered up, t power-up for full shutdown mode should elapse before the next cs falling edge figure 46. normal mode cs 11 6 1 sclk sdata din 1 6 invalid data channel identifier bits + conversion result data into control register data into control register t power-up the p ar tisfullypoweredup once t power-up has elapsed control register is loaded on the first 15 clocks, pm1 = 0, pm0 = 0 to keep the part in normal mode, load pm1 = pm0 = 0 in control register part is in full shutdown part begins to power up on the 15th sclk rising edge as pm1 = pm0 = 0 04864-041 figure 47. exiting full shutdown mode
ad7324 rev. 0 | page 30 of 36 autoshutdown mode as is the case with the autoshutdown mode, the ad7324 enters standby on the 15 th sclk rising edge once the control register is updated (see (pm1 = 1, pm0 = 0) figure 48 ). the part retains information in the registers during standby. once in autostandby mode, the once the autoshutdown mode is selected, the ad7324 auto- matically enters shutdown on the 15 th sclk rising edge. in autoshutdown mode, all internal circuitry is powered down. the ad7324 retains information in the registers during autoshutdown. the track-and-hold is in hold mode during autoshutdown. on the rising cs signal must remain low to keep the part in autostandby mode. the ad7324 remains in standby until it receives a cs rising edge. the adc begins to power up on the cs rising edge. on the cs rising edge, the track-and-hold, which was in hold mode while the part was in standby, returns to track. the power-up time from standby is 700 ns. cs edge, the track-and-hold, which was in hold during shutdown, returns to track as the ad7324 begins to power up. the power-up from autoshutdown is 500 s. the user should ensure that 700 ns have elapsed before bringing when the control register is programmed to transition to autoshutdown mode, it does so on the 15 th sclk rising edge. cs low to attempt a valid conversion. once this valid conversion is complete, the ad7324 again returns to standby on the 15 th sclk rising edge. the figure 48 shows the part entering autoshutdown mode. once in autoshutdown mode, the cs signal must remain low to keep the part in standby mode. cs signal must remain low to keep the part in autoshutdown mode. the ad7324 automatically begins to power up on the cs figure 48 shows the part entering autoshutdown mode. the sequence of events is the same when entering autostandby mode. in rising edge. the t power-up for autoshutdown is required before a valid conversion, initiated by bringing the cs figure 48 , the power management bits are configured for autoshutdown. for autostandby mode, the power management bits, pm1 and pm0, should be set to 0 and 1, respectively. signal low, can take place. once this valid conversion is complete, the ad7324 powers down again on the 15 th sclk rising edge. the cs signal must remain low again to keep the part in autoshutdown mode. autostandby mode (pm1 = 0, pm0 =1) in autostandby mode, portions of the ad7324 are powered down, but the on-chip reference remains powered up. the reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. this mode is similar to autoshutdown, but allows the ad7324 to power up much faster. this allows faster throughput rates to be achieved. cs 11 6 15 1 1615 sclk sdata din valid data valid data data into control register data into control register t power-up control register is loaded on the first 15 clocks, pm1 = 1, pm0 = 0 part enters shutdown mode on the 15th rising sclk edge as pm1 = 1, pm0 = 0 p a rt begins to powe r up on cs rising edge the p a rt is fully powered up once t power-up has elapsed 0 4864-042 figure 48. entering autoshutdown/autostandby mode
ad7324 rev. 0 | page 31 of 36 20 0 0 1000 throughput rate (khz) average power (mw) 18 16 14 12 10 8 6 4 2 100 200 300 400 500 600 700 800 900 20mhz sclk variable sclk v cc =5v v dd /v ss = 12v t a = 25c internal reference 04864-053 power vs. throughput rate the power consumption of the ad7324 varies with throughput rate. the static power consumed by the ad7324 is very low, and a significant power savings can be achieved as the throughput rate is reduced. figure 49 and figure 50 shows the power vs. throughput rate for the ad7324 at a v cc of 3 v and 5 v, respectively. both plots clearly show that the average power consumed by the ad7324 is greatly reduced as the sample frequency is reduced. this is true whether a fixed sclk value is used or if it is scaled with the sampling frequency. figure 49 and figure 50 show the power consumption when operating in normal mode for a fixed 20 mhz sclk and a variable sclk that scales with the sampling frequency. 12 0 0 1100 throughput rate (ksps) average power (mw) 10 8 6 4 2 100 200 300 400 500 600 700 800 900 1000 variable sclk 20mhz sclk v cc =3v v dd /v ss = 12v t a = 25c internal reference 04864-052 figure 50. power vs. throughput rate with 5 v v cc figure 49. power vs. throughput rate with 3 v v cc
ad7324 rev. 0 | page 32 of 36 serial interface figure 51 shows the timing diagram for the serial interface of the ad7324. the serial clock applied to the sclk pin provides the conversion clock and controls the transfer of information to and from the ad7324 during a conversion. data is clocked into the ad7324 on the sclk falling edge. the 3 msbs on the din line are decoded to select which register is being addressed. the control register is a 12-bit register. if the control register is addressed by the 3 msbs, the data on the din line is loaded into the control on the 15 th sclk rising edge. if the sequence register or the range register is addressed, the data on the din line is loaded into the addressed register on the 11 th sclk falling edge. cs the signal initiates the data transfer and the conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state. then the analog input signal is sampled. once the conversion is initiated, it requires 16 sclk cycles to complete. conversion data is clocked out of the ad7324 on each sclk falling edge. data on the dout li ne consists of a leading zero bit, two channel identifier bits, a sign bit, and a 12-bit conversion result. the channel identifier bits are used to indicate which channel corresponds to the conversion result. the leading zero bit is clocked out on the the track-and-hold goes back into track mode on the 14 th sclk rising edge. on the 16 th sclk falling edge, the dout line returns to three-state. if the rising edge of cs occurs before 16 sclk cycles have elapsed, the conversion is terminated, and the dout line returns to three-state. depending on where the cs falling edge, and the first channel identifier bit is clocked out on the first sclk falling edge. cs signal is brought high, the addressed register may be updated. add1 12345 13141516 write reg sel1 reg sel2 lsb msb add0 sign db11 db10 db2 db1 db0 t 2 t 6 t 4 t 9 t 10 t 3 t 7 t 5 t 8 t 1 t quiet t convert sclk cs dout three- state three-state din zero 2 identification bits 04864-036 don?t care figure 51. serial interface timing diagram (control register write)
ad7324 rev. 0 | page 33 of 36 microprocessor interfacing the serial interface on the ad7324 allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the ad7324 with some common microcontroller and dsp serial interface protocols. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (ax0 = tx0), the state of the serial clock is checked. the dsp waits until the sclk has gone high, low, and high again before starting the transmission. if the timer and sclk are chosen, so that the instruction to transmit occurs on or near the rising edge of sclk, data can be transmitted immediately or at the next clock edge. ad7324 to adsp-218x the adsp-21xx family of dsps interface directly to the ad7324 without requiring glue logic. the v drive pin of the ad7324 takes the same supply voltage as that of the adsp-21xx. this allows the adc to operate at a higher supply voltage than its serial interface. the sport0 on the adsp-21xx should be configured as shown in for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value 3, an sclk of 2 mhz is obtained, and eight master clock periods elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks occur between interrupts and, subsequently, between transmit instructions. this situation leads to nonequidistant sampling because the transmit instruction occurs on an sclk edge. if the number of sclks between interrupts is an integer of n, equidistant sampling is implemented by the dsp. table 14 . table 14. sport0 control register setup setting description tfsw = rfsw = 1 alternative framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data word ad7324 to adsp-bf53x isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word the adsp-bf53x family of dsps interface directly to the ad7324 without requiring glue logic, as shown in irfs = 0 figure 53 . the sport0 receive configuration 1 register should be set up as outlined in itfs = 1 table 15 . the connection diagram is shown in figure 52 . the adsp-21xx has tfs0 and rfs0 tied together. tfs0 is set as an output, and rfs0 is set as an input. the dsp operates in alternative framing mode, and the sport0 control register is set up as described in ad7324 1 adsp-bf53x 1 v dd v drive sclk rsclk0 din dt0 dout dr0 cs rfs0 1 additional pins omitted for clarity. 04864-038 table 14 . the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applications, requires equidistant sampling. however, as in this example, the timer interrupt is used to control the sampling rate of the adc and under certain conditions equidistant sampling cannot be achieved. ad7324 1 adsp-21xx 1 sclk sclk0 cs tfs0 rfs0 dout din dt0 dr0 v dd v drive 1 additional pins omitted for clarity. 0 4864-037 figure 53. interfacing the ad7324 to the adsp-bf53x table 15. sport0 receive configuration 1 register setting description rckfe = 1 sample data with falling edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 1 internal rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 1 internal receive clock figure 52. interfacing the ad7324 to the adsp-21xx rspen = 1 receive enable the timer registers are loaded with a value that provides an interrupt at the required sampling interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and, hence, the reading of data. slen = 1111 16-bit data-word tfsr = rfsr = 1
ad7324 rev. 0 | page 34 of 36 application hints layout and grounding the printed circuit board that houses the ad7324 should be designed so that the analog and digital sections are confined to certain areas of the board. this design facilitates the use of ground planes that can easily be separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. all agnd pins on the ad7324 should be connected to the agnd plane. digital and analog ground pins should be joined in only one place. if the ad7324 is in a system where multiple devices require an agnd and dgnd connection, the connection should still be made at only one point. a star point should be established as close as possible to the ground pins on the ad7324. good connections should be made to the power and ground planes. this can be done with a single via or multiple vias for each supply and ground pin. avoid running digital lines under the ad7324 device because this couples noise onto the die. however, the analog ground plane should be allowed to run under the ad7324 to avoid noise coupling. the power supply lines to the ad7324 device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, components, such as clocks, with fast switching signals should be shielded with digital ground and never run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces should be run at right angles to each other. a microstrip technique is the best method, but its use may not be possible with a double- sided board. in this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have a low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic and surface mount types of capacitors. these low esr, low esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
ad7324 rev. 0 | page 35 of 36 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 54. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions show in millimeters ordering guide model temperature range package description package option ad7324bruz C40c to +85c 16-lead tssop ru-16 1 ad7324bruz-reel C40c to +85c 16-lead tssop ru-16 1 ad7324bruz-reel7 C40c to +85c 16-lead tssop ru-16 1 EVAL-AD7324CB evaluation board 2 eval-control brd2 controller board 3 1 z = pb-free part. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration p urposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, the particular adc evaluation board (for exampl e, EVAL-AD7324CB), the eval-control brd2, and a 12 v transformer must be ordered. see the relevant evaluation board technical no te for more information.
ad7324 rev. 0 | page 36 of 36 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04864C0C12/05(0)

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